N phases of divide-by-N clocks with a 1/N duty ratio may be utilized to serialize N bits of parallel data into a serial data stream using a multiplexer. One method of generating N phases of divide-by-N clocks with a 1/N duty ratio is to use a counter and a decoder, as illustrated in FIG. 5. The clock divider circuit 500 depicted in FIG. 5 includes an input 501 receiving a clock signal CK at frequency f at an n-bit counter 502, which counts from 0 to N−1. Counter 502 may be implemented, for example, by an n-bit series of flip-flops, where 3≦N≦2n. A decoder 503 receives the n-bit output of counter 502 and generates N phases of the clock signal CK each at a frequency f/N at outputs 504.
FIG. 6 depicts in greater detail an exemplary implementation of a divide-by-five clock divider 600 utilizing a counter 502 and a decoder 503. The counter 502 is implemented by a series of three flip-flops clocked by the clock signal CK at frequency f, with the inverted outputs of the second and third logically combined by an AND gate, the output of which is passed to the input of the first flip-flop in the series. A three bit output signal is taken from the inverted output of the first flip-flop and the non-inverted outputs of the second and third, then passed to the decoder 503. Decoder 503 includes logical gates (AND gates with selective inputs inverted in the example shown) generating the N clock signal each having non-overlapping asserted phases with a 1/N duty cycle at a frequency f/5.
One disadvantage of the approach depicted and described is that the large load capacitances from the decoding logic 503 decreases the maximum operating frequency. To increase the operating frequency, large buffers that consume substantial power are often inserted in between the counter and the decoder. Another disadvantage is that the unbalanced load capacitances from the counter reset circuit (not shown) and the decoder causes the phases to overlap and/or the duty ration to deviate from the desired value of 1/N at high operating frequencies.
There is, therefore, a need in the art for clock divider dividing a clock signal into N non-overlapping phases with a precise 1/N duty ratio at high operating frequencies.